Walking the Multi-Level Page Table: Translating a Virtual Address to a Physical Address

Between a pointer value and a real location in memory stands a multi-level page table. This topic walks all four levels of a real translation, with page faults, huge pages, and the TLB each taking their place in live measurements.

STARTFINISHVirtual Addresses and 4 KiB Pages: ASLR and the Arithmetic of the Flat Table→STARTFINISHFour Levels of Tables: Splitting a 48-bit Address and Reading the PTE from pagemap→STARTFINISHTwo Fates of a Page Fault: Demand Paging and the TLB→