OLED Display Cache Architecture

Introduction

The OLED cache (framebuffer) is a critical component of the display system. It maintains an off-screen representation of the display content, allowing efficient updates and animations while minimizing I2C traffic.

Cache Dimensions

The OLED cache is organized as:

• Height: CACHED_HEIGHT = 8 pixels (1 byte in vertical compression)
• Width: CACHED_WIDTH = 144 pixels
• Total Pixels: 1152 pixels
• Memory Layout: Packed vertically (8 pixels per byte)

Memory Layout

The cache uses a page-based layout common to SSD1306-compatible displays:

Byte layout (vertical compression):
Bit 7: Page 0, Row 7
Bit 6: Page 0, Row 6
Bit 5: Page 0, Row 5
Bit 4: Page 0, Row 4
Bit 3: Page 0, Row 3
Bit 2: Page 0, Row 2
Bit 1: Page 0, Row 1
Bit 0: Page 0, Row 0

Typical Cache Operations

Setting a Pixel

void set_pixel(int x, int y, int color) {
    if (x < 0 || x >= CACHED_WIDTH || y < 0 || y >= CACHED_HEIGHT * 8) {
        return;  // Out of bounds
    }

    int page = y / 8;      // Which byte (page)
    int bit = y % 8;       // Which bit within byte
    int offset = page * CACHED_WIDTH + x;

    if (color) {
        cache[offset] |= (1 << bit);   // Set pixel
    } else {
        cache[offset] &= ~(1 << bit);  // Clear pixel
    }
}

Updating Display from Cache

void display_refresh(void) {
    for (int page = 0; page < CACHED_HEIGHT; page++) {
        // Set page address command
        write_command(0xB0 | page);

        // Write entire page (144 bytes)
        for (int x = 0; x < CACHED_WIDTH; x++) {
            int offset = page * CACHED_WIDTH + x;
            write_data(cache[offset]);
        }
    }
}

Performance Considerations

• Memory: (CACHED_HEIGHT * 8) * CACHED_WIDTH / 8 bytes = 1152 bytes
• Update Time: Full refresh ~1-2ms at 400kHz I2C
• Partial Updates: Recommended for animations (update only changed regions)

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Updated on 2026-02-03 at 13:21:55 +0000